The present invention relates to a semiconductor device.
SRAM (Static Random Access Memory), which is one of the semiconductor memories, is a so-called non-volatile memory that can temporarily store various data. For example, SRAM is provided in a semiconductor device including a CPU (Central Processing Unit), and the like, to temporarily store data and information generated in various processes of the CPU. In general, low power consumption is required for semiconductor devices. For this reason, the leakage current should be reduced in the SRAM.
For example, Japanese Unexamined Patent Application Publication No. 2004-206745 (Patent Document 1) discloses a semiconductor memory device that can reduce the leakage current of a SRAM circuit and allow the SRAM circuit to operate at a high speed.
More specifically, in a memory array in which a plurality of static type memory cells, each of which includes a drive MOSFET (Metal Oxide semiconductor Field Effect Transistor), a transfer MOSFET, and a load element, are arranged, a semiconductor memory device includes: a switch that controls to couple a source line, which is coupled to a source electrode of the drive MOSFET, to a ground potential line when the memory cell is operated, and controls to disconnect the source line and the ground potential line when the memory cell is in a standby mode; and a source potential control circuit coupled between the source line and the ground potential. When the memory cell is in a standby mode, the source potential control circuit sets the source potential to an intermediate potential between ground potential and power supply potential.